Shift registers are commonly used to drive a display panel, such as a thin-film transistor liquid-crystal display (TFT-LCD) panel. In a typical TFT-LCD display panel, a plurality of pixels are arranged in a two-dimensional array. These pixels are controlled by a plurality of data lines and a plurality of gate lines. The data lines are connected to a data source driver and the gate lines are connected to a gate line driver. A gate line driver comprises a shift register module having a plurality of shift register units connected in a cascade manner such that the output of a shift register unit in a stage is connected to the input of a shift register unit of the subsequent stage. The output of each shift register unit in a shift register module is connected to a gate line of the display panel for sequentially driving the pixel array. All the shift register units in a shift register module are connected to a clock signal (CK), a complementary or inverted clock signal (XCK) and a source voltage (VSS).
A prior art shift register (SR) circuit is shown in FIG. 1. As shown in FIG. 1, the SR circuit 2 comprises four transistors Q1-Q4 and an inverter 20. The first transistor Q1 has a gate coupled to the inverted clock signal XCK and a first source/drain coupled to a signal output (N−1) from a previous-stage shift-register unit. The inverter 20 has an input terminal coupled to the first source/drain of the first transistor Q1. The second transistor Q2 has a gate coupled to a second source/drain of the first transistor Q1; a first source/drain coupled to the clock signal CK and a second source/drain coupled to an output terminal N. The third transistor Q3 has a gate coupled to the output terminal of the inverter 20; a first source/drain coupled to the output terminal N and a second source/drain coupled to the source voltage VSS. The fourth transistor Q4 has a gate coupled to a signal output N+1 from a next-stage shift-register unit; a first source/drain coupled to the output terminal N and a second source/drain coupled to the source voltage VSS. In the SR circuit as shown in FIG. 1, the point A between the gate of the second transistor Q2 and the second source/drain of the first transistor Q1 is known as a bootstrap point. The bootstrap point A and the second source/drain of the second transistor Q2 is capacitively coupled as indicated by the capacitor C.
FIG. 2 is a timing chart showing the SR output of the current stage N, the SR output of the previous stage N−1, and the SR output of the next stage N+1 in relation to the clock signal CK, the inverted clock signal XCK along with the voltage level at the bootstrap point A.
The operation of the SR circuit is as follows. When the inverted clock signal XCK is at a high voltage level, the first transistor Q1 is turned on. The previous-stage shift-register unit (N−1) outputs a high voltage level signal through the first transistor Q1 to turn on the second transistor Q2. As a result, the output terminal (N) outputs a clock signal to the next-stage shift-register unit (N+1). In addition, the fourth transistor Q4 is switched on by the output signal of the next-stage shift-register unit (N+1). When the fourth transistor Q4 is turned on, the output terminal (N) outputs a low voltage level signal.
When the output terminal (N−1) of the previous-stage shift-register unit outputs a low voltage level signal to the inverter 20, the inverter 20 outputs a high voltage level signal to the third transistor Q3. Thus, the output terminal (N) is held at a low voltage level.
When the first transistor Q1 is turned on during the time period t1, the voltage level of the bootstrap point A and the output signal N are almost equal with a difference of the transistor threshold voltage Vth (see FIG. 3). When the inverted clock signal XCK is at a low voltage level, the bootstrap point A is in a floating state. According to the feed-though voltage drop theory, the voltage difference between the gate and the first source/drain of the second transistor Q2 is held steady. When the clock signal Ck is at a high voltage level during the time period t2, the bootstrap point A is at a higher voltage level Vb1 (see FIG. 3). During the time period t3, the output of the next stage shift-register unit (N+1) is high, and the voltage at the bootstrap point A is discharged to a low level.
As shown in FIG. 3, the voltage level at the bootstrap point A is equal to Vb1 during the time period t2, and Vb1 is given byVb1=2×(VDD−VSS)−Vth where VDD is the drain voltage which is substantially equal the voltage level of CK when CK is at a high level, and VDD is higher than VSS. Because the voltage level Vb1 during the time period t2 is relatively high as compared to the voltage level at (N−1)OUT, the source-drain voltage imposes a high stress on the first transistor Q1. This stress could damage the first transistor Q1 and cause the voltage drift in the SR unit.
Likewise, in an electronic circuit that uses a first transistor as a switch to provide a bias voltage level to the gate of a second transistor at a clock cycle and to maintain the charge at that gate at a complementary clock cycle, the voltage level at the gate, or the bootstrap point, gives rise to a relative high source-drain voltage of the first transistor at the complementary clock cycle. This source-drain voltage imposes a high stress on the first transistor.
It is advantageous and desirable to provide a method and device to reduce the voltage level at the bootstrap point and thus the source-drain voltage of the first transistor in such an electronic circuit.